The phase locked loop (PLL) circuit is a feedback control circuit which may be analog or digital. A phase detector develops an adjustment signal based on comparison between the output of a local voltage controlled oscillator (VCO) and a reference clock input signal. The adjustment signal is processed to provide a modified input to the VCO which results in a phase or frequency modification to the oscillator output signal. Phase locked loop circuits are common building blocks in custom integrated circuitry providing, for example, synchronization solutions in a wide variety of gigaHertz (GHz) rate data communications applications. However, in some applications, such as cellular communications base stations, high speed precision has required use of discrete components.
Conventionally, PLL's can be categorized as analog or digital, but numerous variants exist, including the combination of digital phase detection with the phase detection output processed through a charge pump and an analog loop filter to provide a voltage input to the VCO. With the phase locked loop (PLL) circuit 10 not incorporating charge pump circuitry to store charge in a capacitor for input to the voltage controlled oscillator, the impedance characteristics of the replica circuit 65 and the VCO 12 are so matched that current-voltage characteristics of these two impedance devices can be within five percent of one another throughout the voltage operating range of the VCO. With substantially matched impedance characteristics of the VCO 12 and the replica circuit 65, the system does not incorporate charge pump circuitry to store charge in a capacitor for input to the voltage controlled oscillator.
The impedance characteristics of the replica circuit 65 can so closely follow the impedance characteristics of the voltage controlled oscillator as a function of voltage level as to allow a voltage level to be switched between the subcircuit 65 and the voltage controlled oscillator 12 without creating voltage spikes, when a voltage level is switched between the replica circuit 65 and the VCO. More generally, when a voltage level is switched between the replica circuit and the VCO 12, voltage spikes can be controlled to a range between zero and two percent of the operating voltage applied to the VCO. A full digital PLL solution comprises a digital phase detector, a digital filter and a numerically controlled oscillator. Both analog and digital implementations typically generate a proportional component and an integral component for, respectively, delivering phase and frequency feedback control to the oscillator.
FIG. 1A is a high level diagram of a conventional PLL incorporating a charge pump an analog loop filter and a trans-conductance (Gm) amplifier as more fully illustrated in FIG. 1B. A phase-frequency detector (PFD) receives a reference clock input signal of desired frequency and a feedback signal from a VCO. The PFD may be one of numerous designs, including types based on exclusive OR gates or flip flops, which output a pulse signal proportional to positive or negative phase and frequency differences between the clock signal and the feedback signal.
In the past, it has been necessary to provide the charge pump, loop filter, and Gm amplifier to translate the full swing up and down signals from the PFD to the VCO. The signals from the PFD turn switches in the charge pump on and off to provide currents, creating a voltage differential, ΔV, across the resistor R. This small signal voltage, ΔV, is then passed into the Gm amplifier, sometimes referred to as a voltage to current converter. The current output from the Gm goes into the VCO. Through this process, gain is realized through the product of the charge pump current and resistance of R, as well as operation of the Gm amplifier. However, the analog PLL requires a large passive device in a monolithic process and results in a path for noise to enter the VCO.
The VCO may be a three stage ring oscillator circuit having three inverters I1, I2, I3 coupled in series as shown in FIG. 1C. Assuming a predetermined bias voltage, the circuit oscillates at a frequency, f, having an associated period 1/f. For this three stage ring, the group delay (or the phase shift) of all 3 stages is 360 degrees. Hence, this means each stage I1, I2, I3 has a delay of 120 degrees and, due to the phase shift, the nodes labeled N1, N2, N3 will be at different potentials at any instant in time. For example, when one of the nodes is close to VDD, another node will be close to ground (VSS) and the other node will be at a potential between VDD and ground.
Generally, the desired VCO frequency, f, is a multiple, N, of the reference clock signal frequency, and is factored by the block DIV/N accordingly to provide the suitable feedback signal for comparison to be made by the PFD. This results in a phase difference output signal which may comprise a pulse width having time duration in proportion to the phase difference. A charge pump receives the phase difference output signal and generates current in proportion to the phase difference. The current output by the charge pump is fed through an analog loop filter to the VCO. The design of the loop filter affects response time, bandwidth and stability. The combination of the charge pump and the loop filter provides two components of signal to the VCO: a pulse component in proportion to the phase difference, and an integral component which affects the frequency adjustment.
An advantage of the analog PLL is low jitter. However, with increased demands for higher speed precision, even the relatively low noise analog PLL implementations considered acceptable at lower data rates may be too noise sensitive in some gigahertz data communications. For example, tuning of the loop filter component for a desired response time and stability in an analog PLL can still result in added noise. Generally, it is desirable to develop designs which further reduce the impact of noise sources. Another limitation of analog PLL circuits is that the analog charge pumps and loop filters have wide range voltage tuning requirements. These are becoming increasingly difficult to meet as manufacturing technologies have moved past the 45 nanometer node to 28 nm technologies and toward, for example, 10 nm linewidths. When fabricating analog PLLs in deep nanometer technologies there are also concerns about relatively high capacitor leakage rates and, generally, disadvantages due to an inability to scale the sizes of analog components with the smaller digital components.
FIG. 2 illustrates an example of an all digital PLL. Common to all fully digital PLLs, analog circuit blocks are replaced by converting signals received from the PFD into digital signals, using quantizers or analog-to-digital converters. In lieu of a charge pump and an analog loop filter, the digital implementation performs digital conversions of the output signals generated by the PFD. Elimination of the capacitor permits better scaling to small fabrication geometries and reduces sensitivity to process variations. The illustrated digital PLL has a proportional path, for adjusting the phase of the VCO, which is distinct from a frequency adjusting integral path. The proportional and integral paths undergo separate digital-to-analog conversions for input to the VCO because they each may require conversion of a different number of bits. Advantageously, elimination of the analog charge pump and analog loop filter enhances scalability and avoids sensitivity problems which analog components exhibit to minor process variations. On the other hand, quantization of the proportional and integral tuning paths introduces jitter, e.g., static phase offset, which precludes use of digital PLLs when timing precision is essential.